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19-2029; rev 2; 10/12 max9205/max9207 10-bit bus lvds serializers evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maximintegrated.com. general description the max9205/max9207 serializers transform 10-bit- wide parallel lvcmos/lvttl data into a serial high- speed bus low-voltage differential signaling (lvds) data stream. the serializers typically pair with deserial- izers like the max9206/max9208, which receive the serial output and transform it back to 10-bit-wide paral- lel data. the max9205/max9207 transmit serial data at speeds up to 400mbps and 660mbps, respectively, over pcb traces or twisted-pair cables. since the clock is recov- ered from the serial data stream, clock-to-data and data-to-data skew that would be present with a parallel bus are eliminated. the serializers require no external components and few control signals. the input data strobe edge is selected by tclk_r/f. pwrdn is used to save power when the devices are not in use. upon power-up, a synchroniza- tion mode is activated, which is controlled by two sync inputs, sync1 and sync2. the max9205 can lock to a 16mhz to 40mhz system clock, while the max9207 can lock to a 40mhz to 66mhz system clock. the serializer output is held in high impedance until the device is fully locked to the local system clock, or when the device is in power- down mode. both the devices operate from a single +3.3v supply, are specified for operation from -40? to +85?, and are available in 28-pin ssop packages. applications features standalone serializer (vs. serdes) ideal for unidirectional links framing bits for deserializer resync allow hot insertion without system interruption lvds serial output rated for point-to-point and bus applications wide reference clock input range 16mhz to 40mhz (max9205) 40mhz to 66mhz (max9207) low 140ps (pk-pk) deterministic jitter (max9207) low 34ma supply current (max9205) 10-bit parallel lvcmos/lvttl interface up to 660mbps payload data rate (max9207) programmable active edge on input latch pin-compatible upgrades to ds92lv1021 and ds92lv1023 pcb or twisted pair tclk pll pll en en pwrdn input latch parallel-to-serial output latch serial-to-parallel timing and control timing and control clock recovery rclk lock sync 1 sync 2 out+ out- in+ in- 100? 100? tclk_r/f rclk_r/f refclk out_ in_ 10 10 bus lvds max9205 max9207 max9206 max9208 ordering information part temp range pin- package ref clock range (mhz) max9205 eai+ -40? to +85? 28 ssop 16 to 40 m ax 9205e ai/v + -40? to +85? 28 ssop 16 to 40 max9207 eai+ -40? to +85? 28 ssop 40 to 66 pin configuration and functional diagram appear at end of data sheet. typical application circuit cellular phone base stations add drop muxes digital cross-connects dslams network switches and routers backplane interconnect + denotes a lead(pb)-free/rohs-compliant package. /v denotes an automotive qualified part.
max9205/max9207 10-bit bus lvds serializers 2 maxim integrated absolute maximum ratings dc electrical characteristics (v avcc = v dvcc = +3.0v to +3.6v, r l = 27? ?% or 50? ?%, c l = 10pf, t a = -40? to +85?. typical values are at v avcc = v dvcc = +3.3v and t a = +25?, unless otherwise noted.) (notes 2, 3, 4) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. avcc, dvcc to gnd..........................?0.3v to +4.0v in_, sync1, sync2, en, tclk_r/f, tclk, pwrdn to gnd......................................-0.3v to (v cc + 0.3v) out+, out- to gnd .............................................-0.3v to +4.0v output short-circuit duration.....................................continuous continuous power dissipation (t a = +70?) 28-pin ssop (derate 9.5mw/? above +70?) ..........762mw storage temperature range .............................-65? to +150? junction temperature ......................................................+150? operating temperature range ...........................-40? to +85? esd protection (human body model, out+, out-) ...........?kv lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units lvcmos/lvtll logic inputs (in0 to in9, en, sync1, sync2, tclk, tclk_r/ f , pwrdn ) high-level input voltage v ih 2.0 v cc v low-level input voltage v il gnd 0.8 v input current i in v in_ = 0v or v _vcc -20 +20 ? bus lvds outputs (out+, out-) r l = 27 ? 200 286 400 mv differential output voltage v od figure 1 r l = 50 ? 250 460 600 mv change in v od between complementary output states ? v od figure 1 1 35 mv output offset voltage v os figure 1 0.9 1.15 1.3 v change in v os between complementary output states ? v os figure 1 3 35 mv output short-circuit current i os v out+ or v out- = 0v, in0 to in9 = pwrdn = en = high -13 -15 ma output high-impedance current i oz v pwrdn or v en = 0.8v, v out+ or v out- = 0v or v _vcc -10 +10 ? power-off output current i ox v _vcc = 0v, v out+ or v out- = 0v or 3.6v -10 +10 ? power supply 16mhz 23 35 max9205 40mhz 34 45 40mhz 32 50 supply current i cc r l = 27 _ or 50_ worst-case pattern (figures 2, 4) max9207 66mhz 45 60 ma power-down supply current i ccx pwrdn = low 8 ma note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . package thermal characteristics (note 1) ssop junction-to-ambient thermal resistance ( ja )...............68?/w junction-to-case thermal resistance ( jc )......................25?/w
max9205/max9207 10-bit bus lvds serializers 3 maxim integrated ac electrical characteristics (v avcc = v dvcc = +3.0v to +3.6v, r l = 27? ?% or 50? ?%, c l = 10pf, t a = -40? to +85?. typical values are at v avcc = v dvcc = +3.3v and t a = +25?, unless otherwise noted.) (notes 3, 5) parameter symbol conditions min typ max units transmit clock (tclk) timing requirements max9205 16 40 mhz tclk center frequency f tccf max9207 40 66 mhz tclk frequency variation tcfv -200 200 ppm max9205 25 62.5 tclk period t tcp max9207 15.15 25 ns tclk duty cycle tcdc 40 60 % tclk input transition time t clkt figure 3 3 6 ns tclk input jitter t jit 150 ps (rms) switching characteristics r l = 27 150 300 400 low-to-high transition time t lht figure 4 r l = 50 150 350 500 ps r l = 27 150 300 400 high-to-low transition time t hlt figure 4 r l = 50 150 350 500 ps in_ setup to tclk t s figure 5 1 ns in_ hold from tclk t h figure 5 3 ns output high state to high- impedance delay t hz figures 6, 7 4.5 10 ns output low state to high- impedance delay t lz figures 6, 7 4.5 10 ns output high impedance to high-state delay t zh figures 6, 7 4.5 10 ns output high impedance to low-state delay t zl figures 6, 7 4.5 10 ns sync pulse width t spw 6 x t tcp ns pll lock time t pl figure 7 2048 x t tcp 2049 x t tcp ns bus lvds bit width t bit t tcp /12 ns serializer delay t sd figure 8 t tcp / 6 (t tcp /6) + 5 ns
typical operating characteristics (v avcc = v dvcc = +3.3v, r l = 27?, c l = 10pf, t a = +25?, unless otherwise noted.) max9205/max9207 10-bit bus lvds serializers 4 maxim integrated 10 30 20 40 50 3.0 3.3 3.6 worst-case pattern supply current vs. supply voltage max9205 toc01 supply voltage (v) supply current (ma) tclk = 40mhz max9205 10 30 20 40 50 3.0 3.3 3.6 worst-case pattern supply current vs. supply voltage max9205 toc01 supply voltage (v) supply current (ma) tclk = 40mhz max9205 ac electrical characteristics (continued) (v avcc = v dvcc = +3.0v to +3.6v, r l = 27? ?% or 50? ?%, c l = 10pf, t a = -40? to +85?. typical values are at v avcc = v dvcc = +3.3v and t a = +25?, unless otherwise noted.) (notes 3, 5) note 2: current into a pin is defined as positive. current out of a pin is defined as negative. all voltages are referenced to ground except v od , ? v od , and v os . note 3: c l includes scope probe and test jig capacitance. note 4: parameters 100% tested at t a = +25?. limits over operating temperature range guaranteed by design and characterization. note 5: ac parameters are guaranteed by design and characterization. parameter symbol conditions min typ max units 16mhz 200 max9205 40mhz 140 40mhz 140 deterministic jitter (figure 9) t djit max9207 66mhz 140 ps (pk-pk) 16mhz 13 max9205 40mhz 9 40mhz 9 random jitter (figure 10) t rjit max9207 66mhz 6 ps (rms)
max9205/max9207 10-bit bus lvds serializers 5 maxim integrated pin description pin name function 1, 2 sync 1, sync 2 lvcmos/lvttl logic inputs. the two sync pins are ored. when at least one of the two pins are asserted high for at least six cycles of tclk, the serializer initiates a transmission of 1024 sync patterns. if held high after 1024 sync patterns have been transmitted, sync patterns continue to be sent until the sync pin is asserted low. toggling a sync pin after six tclk cycles high and before 1024 sync patterns have been transmitted does not affect the output of the 1024 sync patterns. 3?2 in0?n9 lvcmos/lvttl data inputs. data is loaded into a 10-bit latch by the selected tclk edge. 13 tclk_r/ f lvcmos/lvttl logic input. high selects a tclk rising-edge data strobe. low selects a tclk falling-edge data strobe. 14 tclk lvcmos/lvttl reference clock input. the max9205 accepts a 16mhz to 40mhz clock. the max9207 accepts a 40mhz to 66mhz clock. tclk provides a frequency reference to the pll and strobes parallel data into the input latch. 15, 16 dgnd digital circuit ground. connect to ground plane. 17, 26 avcc analog circuit power supply (includes pll). bypass avcc to ground with a 0.1? capacitor and a 0.001? capacitor. place the 0.001? capacitor closest to avcc. 18, 20, 23, 25 agnd analog circuit ground. connect to ground plane. 19 en lvcmos/lvttl logic input. high enables serial data output. low puts the bus lvds output into high impedance. 21 out- inverting bus lvds differential output 22 out+ noninverting bus lvds differential output 24 pwrdn lvcmos/lvttl logic input. low puts the device into power-down mode and the output into high impedance. 27, 28 dvcc digital circuit power supply. bypass dvcc to ground with a 0.1? capacitor and a 0.001? capacitor. place the 0.001? capacitor closest to dvcc. detailed description the max9205/max9207 are 10-bit serializers designed to transmit data over balanced media that may be a standard twisted-pair cable or pcb traces at 160mbps to 660mbps. the interface may be double-terminated point-to-point or a heavily loaded multipoint bus. the characteristic impedance of the media and connected devices can range from 100? for a point-to-point inter- face to 54? for a heavily loaded multipoint bus. a dou- ble-terminated point-to-point interface uses a 100?-termination resistor at each end of the interface, resulting in a load of 50?. a heavily loaded multipoint bus requires a termination as low as 54? at each end of the bus, resulting in a termination load of 27?. the serializer requires a deserializer such as the max9206/max9208 for a complete data transmission application. a high-state start bit and a low-state stop bit, added internally, frame the 10-bit parallel input data and ensure a transition in the serial data stream. therefore, 12 serial bits are transmitted for each 10-bit parallel input. the max9205 accepts a 16mhz to 40mhz refer- ence clock, producing a serial data rate of 192mbps (12 bits x 16mhz) to 480mbps (12 bits x 40mhz). the max9207 accepts a 40mhz to 66mhz reference clock, producing 480mbps to 792mbps. however, since only 10 bits are from input data, the actual throughput is 10 times the tclk frequency. to transmit data, the serializers sequence through three modes: initialization mode, synchronization mode, and data transmission mode.
max9205/max9207 10-bit bus lvds serializers 6 maxim integrated initialization mode when v cc is applied, the outputs are held in high impedance and internal circuitry is disabled by on-chip power-on-reset circuitry. when the supply voltage reaches 2.35v, the pll starts to lock to a local refer- ence clock (16mhz to 40mhz for max9205 and 40mhz to 66mhz for max9207). the reference clock, tclk, is provided by the system. a serializer locks within 2049 cycles of tclk. once locked, a serializer is ready to send data or sync patterns depending on the levels of sync 1 and sync 2. synchronization mode to rapidly synchronize with a deserializer, sync pat- terns can be sent. a sync pattern is six consecutive ones followed by six consecutive zeros repeating every tclk period. when one or both sync inputs are asserted high for at least six cycles of tclk, the serial- izer will initiate the transmission of 1024 sync patterns. the serializer will continue to send sync patterns if either of the sync input pins remains high. toggling one sync input with the other sync input low before 1024 sync patterns are output does not interrupt the output of the 1024 sync patterns. data transmission mode after initialization, both sync input pins must be set low by users or through a control signal from the dese- rializer before data transmission begins. provided that sync inputs are low, input data at in0? are clocked into the serializer by the tclk input. setting tclk_r/f high selects the rising edge of tclk for data strobe and low selects the falling edge. if either of the sync inputs goes high for six tclk cycles at any time during data transmission, the data at in0? are ignored and sync patterns are sent for at least 1024 tclk cycles. a start bit high and a stop bit low frame the 10-bit data and function as the embedded clock edge in the serial data stream. the serial rate is the tclk frequency times the data and appended bits. for example, if tclk is 40mhz, the serial rate is 40 x 12 (10 + 2 bits) = 480mbps. since only 10 bits are from input data, the payload rate is 40 x 10 = 400mbps. power-down power-down mode is entered when the pwrdn pin is driven low. in power-down mode, the pll of the serial- izer is stopped and the outputs (out+ and out-) are in high impedance, disabling drive current and also reducing supply current. when pwrdn is driven high, the serializer must reinitialize and resynchronize before data can be transferred. on power-up, in order for the max9205/max9207 to initialize correctly, pwrdn should remain below 0.7v until pclk is stable and all power sup- plies are within specification. high-impedance state the serializer output pins (out+ and out-) are held in high impedance when the supply voltage is first applied and while the pll is locking to the local refer- ence clock. setting en or pwrdn low puts the device in high impedance. after initialization, en functions asynchronously. for example, the serializer output can be put into high impedance while sync patterns are being sent without affecting the internal timing of the sync pattern generation. however, if the serializer goes into high impedance, a deserializer loses pll lock and needs to resynchronize before data transfer can resume. table 1. input /output function table inputs outputs en pwrdn sync 1 sync 2 out+, out- hh when either or both sync 1 and sync 2 are held high for at least six tclk cycles synchronization mode. sync patterns of six 1s and six 0s are transmitted every tclk cycle for at least 1024 tclk cycles. data at in0? are ignored. hh l l data transmission mode. in0? and 2 frame bits are transmitted every tclk cycle. xl x x lx x x output in high-impedance. x = don? care.
max9205/max9207 10-bit bus lvds serializers 7 maxim integrated applications information power-supply bypassing bypass avcc with high-frequency surface-mount ceramic 0.1? and 0.001? capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to avcc. bypass dvcc with high-fre- quency surface-mount ceramic 0.1? and 0.001? capacitors in parallel as close to the device as possi- ble, with the smaller valued capacitor closest to dvcc. differential traces and termination output trace characteristics affect the performance of the max9205/max9207. use controlled-impedance media and terminate at both ends of the transmission line in the media's characteristic impedance. termination with a single resistor at the end of a point- to-point link typically provides acceptable performance. however, the max9205/max9207 output levels are specified for double-terminated point-to-point and mul- tipoint applications. with a single 100? termination, the output swing is larger. avoid the use of unbalanced cables such as ribbon or simple coaxial cable. balanced cables such as twisted pair offer superior signal quality and tend to generate less emi due to canceling effects. balanced cables tend to pick up noise as common mode, which is rejected by a differential receiver. eliminate reflections and ensure that noise couples as common mode by running the differential traces close together. reduce skew by matching the electrical length of the traces. excessive skew can result in a degradation of magnetic field cancellation. the differential output signals should be routed close to each other to cancel their external magnetic field. maintain a constant distance between the differential traces to avoid discontinuities in differential impedance. avoid 90 turns and minimize the number of vias to fur- ther prevent impedance discontinuities. out+ out- v od v os r l 2 r l 2 figure 1. output voltage definitions tclk odd in_ even in_ tclk_r/f = low figure 2. worst-case i cc test pattern tclk t clkt 10% 90% 90% 10% t clkt 0 3v figure 3. input clock transition time requirement
max9205/max9207 10-bit bus lvds serializers 8 maxim integrated v diff v diff = 0 t hlt 20% 80% 80% 20% t lht out+ 10pf 10pf out- r l v diff = (out+) - (out-) figure 4. output load and transition times tclk in_ 1.5v 1.5v 1.5v t h t s t tcp 1.5v timing shown for tclk_r/f = low 1.5v figure 5. data input setup and hold times 1.5v 1.5v t lz t hz t zl t zh 3v 0 1.1v v ol v oh out 1.1v 50% 50% 50% 50% en out+ out- parasitic package and trace capacitance +1.1v 10pf 13.5? 13.5? 10pf en figure 6. high-impedance test circuit and timing
max9205/max9207 10-bit bus lvds serializers 9 maxim integrated pwrdn tclk out t pl active 2.0v 0.8v 1.5v t hz or t lz t zh or t zl sync 1 = sync 2 = low en = high tclk_r/f = high high impedance high impedance figure 7. pll lock time and pwrdn high-impedance delays tclk out in in0 - in9 symbol n in0 - in9 symbol n + 1 t sd start bit v diff = 0 v diff = (out+) - (out-) tclk_ r/f = high 1.5v stop bit start bit stop bit out0 - out9 symbol n+1 out0 - out9 symbol n timing shown for tclk_r/f = high figure 8. serializer delay (out+) - (out-) waveform superimposed random data o differential t djit figure 9. definition of deterministic jitter (t djit ) (out+) - (out-) waveform "clock" pattern (1010...) t rjit t rjit o differential figure 10. definition of random jitter (t rjit )
max9205/max9207 10-bit bus lvds serializers 10 maxim integrated topologies the serializers can operate in a variety of topologies. examples of double-terminated point-to-point, mul- tidrop, point-to-point broadcast, and multipoint topolo- gies are shown in figures 11 through 14. use 1% surface-mount termination resistors. a point-to-point connection terminated at each end in the characteristic impedance of the cable or pcb traces is shown in figure 11. the total load seen by the serializer is 50? . the double termination typically reduces reflections compared to a single 100? termi- nation. a single 100? termination at the deserializer input is feasible and will make the differential signal swing larger. a serializer located at one end of a backplane bus dri- ving multiple deserializers in a multidrop configuration is shown in figure 12. a 54? resistor at the far end ter- minates the bus. this topology allows ?roadcast?of data with a minimum of interconnect. 100? parallel data out parallel data in max9206 max9208 max9205 max9207 100? serialized data figure 11. double-terminated point-to-point 54? asic asic asic asic asic max9205 max9207 max9206 max9208 max9206 max9208 max9206 max9208 max9206 max9208 figure 12. multidrop
max9205/max9207 10-bit bus lvds serializers 11 maxim integrated 100? 100? asic asic asic 100? 100? max9205 max9207 max9150 repeater max9206 max9208 max9206 max9208 figure 13. point-to-point broadcast using max9150 repeater a point-to-point version of the multidrop bus is shown in figure 13. the low-jitter max9150 10-port repeater is used to reproduce and transmit the serializer output over 10 double-terminated point-to-point links. compared to the multidrop bus, more interconnect is traded for more robust hot-plug capability. the repeater eliminates nine serializers compared to 10 individual point-to-point serializer-to-deserializer con- nections. since repeater jitter subtracts from the serial- izer-deserializer timing margin, a low-jitter repeater is essential in most high data rate applications. multiple serializers and deserializers bused over a dif- ferential serial connection on a backplane are shown in figure 14. the second serializer can be a backup to the primary serializer. the typical close spacing (1in or less) of cards on a backplane reduces the characteris- tic impedance by as much as half the initial, unloaded value. termination resistors that match the loaded char- acteristic impedance are required at each end of the bus. the total loaded seen by the serializer is 27 ? in this case. board layout for bus lvds applications, a four-layer pcb that pro- vides separate power, ground, and input/output signals is recommended. separate lvttl/lvcmos and bus lvds signals from each other to prevent coupling into the bus lvds lines.
max9205/max9207 10-bit bus lvds serializers 12 maxim integrated 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view max9205 max9207 sync1 sync2 in0 in1 in2 in3 tclk in4 in5 in6 in7 in8 in9 tclk_r/f dgnd dgnd avcc agnd en agnd out- out+ agnd pwrdn agnd avcc dvcc dvcc + ssop out+ out- en 10 in_ tclk_r/f tclk sync 1 sync 2 pll input latch parallel-to-serial timing and control pwrdn max9205 max9207 functional diagram pin configuration 54? asic asic asic asic asic 54? max9205 max9207 max9205 max9207 max9206 max9208 max9206 max9208 max9206 max9208 figure 14. multipoint chip information process: cmos package information for the latest package outline information and land patterns (foot- prints), go to www.maximintegrated.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 28 ssop a28+4 21-0056 90-0095
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 ________________________________ 13 2012 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. max9205/max9207 10-bit bus lvds serializers revision history revision number revision date description pages changed 0 5/01 initial release ? 1 11/10 updated ordering information , absolute maximum ratings , and package 1, 2, 13 2 10/12 added package thermal characteristics section and updated the electrical characteristics and the power-down sections 2?4, 6

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